1. Field of the Invention
The present invention relates to a delay locked loop circuit, and more particularly to a delay locked loop circuit having an improved processing speed and a reduced area for elements of the circuit, so that the delay locked loop circuit can operate in a wide range of a frequency through.
2. Description of the Prior Art
As generally known in the art, a semiconductor memory device has a phase difference between an externally inputted clock (external clock) and an internal clock due to several causes. That is, a phase of the external clock is delayed due to line loading and a clock input buffer receiving the external clock inputted into the semiconductor memory device. Also, a phase of the external clock is delayed due to line loading, an output buffer which receives internal cell data in order to output the internal cell data to the outside of the semiconductor memory device, and other logic circuits. As described above, a phase delayed by circuits accommodated in the semiconductor memory device is called “skew”. A delayed locked loop circuit compensates for a delay of such a phase.
Such a delayed locked loop circuit prevents occurrence of a phase difference between a clock and data, which are outputted to the outside of the semiconductor memory device from the inside thereof. Accordingly, the delayed locked loop circuit synchronizes a clock used in the semiconductor memory device with a chip-set clock and sends cell data to an external chip-set without errors. That is, in a data read operation, the delayed locked loop circuit equalizes a timing of an externally inputted clock with the timing at which data read from a cell in a semiconductor memory device pass through a data output buffer on the basis of the external clock.
In particular, since the delayed locked circuit used for high-speed synchronization memory devices such as DDR SDRAMs determines an operation frequency band of the memory devices and exerts serious influence on an operation time characteristic, the high-speed synchronization memory devices include a high-performance delay locked loop circuit having a wide frequency band and a low jitter characteristic.
FIG. 1 illustrates a block diagram of a typical delayed locked loop circuit.
As shown in FIG. 1, the delay locked loop circuit includes a clock buffer 101 for receiving external clock signals (CLK and CLKB), a delay line 102 for receiving an output signal (RCK (rising clock) or FCK (falling clock)) of the clock buffer 101, a clock divider 105 for dividing an output signal of the clock buffer 101, a clock divider 109 for dividing an output signal IRCK from among output signals IRCK and IFCK of the delay line 102, a replica delay part 108 for delaying an output signal of the clock divider 109 by a predetermined time td1+td2, a phase comparator 106 for comparing a phase of an output signal FBCLK outputted from the replica delay part 108 with a phase of an output signal REFLK of the clock divider 105, a delay control part 107 for controlling a delay time of the delay line 102 by receiving an output signal of the phase comparator 106, and a clock driver 103 for receiving the output signal IRCK or IFCK of the delay line 102. An output signal RCKDLL or FCKDLL of the clock driver 103 controls the operation of a data output driver 104.
As shown in FIG. 1, the CLK refers to an external clock signal, and the CLKB refers to an inverted external clock signal having a phase inverse to the CLK.
The clock buffer 101 is a buffer circuit for receiving the external clock signals CLK and CLKB and converting a voltage level of the clock buffer into a voltage level (e.g., CMOS level) used in a semiconductor device.
The delay line 102 is a circuit for delaying the output signal RCK or FCK of the clock buffer 101 by a predetermined time. Generally, the delay line 102 includes a plurality of unit delay circuits, and a delay time of the delay line 102 is controlled by the delay control part 107.
The clock driver 103 having a powerful driving force is a clock driving circuit which receives the output signal IRCK or IFCK of the delay line 103 and generates a driving signal for driving the data output driver 104.
The data output driver 104 outputs data to the outside thereof in response to the output signal RCKDLL or FCKDLL of the clock driver 103.
The clock divider 105 generates a predetermined reference clock by dividing a clock signal RCK or FCK outputted from the clock buffer 101 at the ratio of 1/n (generally, n may be ‘4’, ‘8’, ‘16’, etc., as an integer).
The clock divider 109 is a circuit for dividing an output signal IRCK frequency of the delay line 102. Generally, the clock divider has the same circuit structure as the clock divider 105.
The replica delay part 108 is a delay circuit having a delay time tD1 and tD2 obtained by adding a delay time tD1 of the clock buffer 101 to a delay time tD2 of the data output driver 104.
The phase comparator 106 compares a phase of the output signal REFCLK of the clock divider 105 with a phase of a feedback signal, which is an output signal of the replica delay part 90. That is, the phase comparator 106 controls the delay control part 107 by calculating a delay time difference between tow signals REFCLK and FBCLK.
The delay control part 107 controls a delay time of the delay line 102.
For reference, as shown in FIG. 1, tCK denotes a period of the external clock, the RCK (rising clock) signal, which is the output signal of the clock buffer 101, corresponds to the external clock signal CLK, and the FCK (falling clock), which is the output signal of the clock buffer 101, corresponds to the external clock signal CLKB. The IRCK (internal rising clock) signal, which is the output signal of the delay line 102, is a delay signal of the signal RCK, and the IFCK (internal falling clock) signal, which is the output signal of the delay line 102, is a delay signal of the FCK signal.
As shown in FIG. 1, the clock divider 105 receives only the RCK signal from among the output signals of the clock buffer 101. Also, the clock divider 109 receives only the IRCK signal from among output signals of the delay line 102.
Hereinafter, a basic operation of the delay locked loop circuit will be described.
The phase comparator 106 compares a phase of the output signal REFCLK of the clock divider 105 with a phase of the output signal FBCK of the replica delay part 90, and sends a predetermined signal to the delay control part 107. The control part 107 controls the delay line 102 in such a manner that the delay line 102 adjusts a delay time in order to minimize a phase difference. The control procedure is repeated until the phase difference is removed.
However, a conventional delay locked loop circuit shown in FIG. 1 has the following problems.
1. It is necessary to increase the number of unit delay circuits included in the delay line 102 in order to operate the delay locked loop circuit in a wide frequency band.
2. If the number of the unit delay circuits is increased, an area occupied by the delay line 102 is large.
3. The more the number of the unit delay circuits is, the more the power consumption is.